/**
 * SyntaxHighlighter
 * http://alexgorbatchev.com/
 *
 * SyntaxHighlighter is donationware. If you are using it, please donate.
 * http://alexgorbatchev.com/wiki/SyntaxHighlighter:Donate
 *
 * @version
 * 2.0.296 (March 01 2009)
 * 
 * @copyright
 * Copyright (C) 2004-2009 Alex Gorbatchev.
 *
 * @license
 * This file is part of SyntaxHighlighter.
 * 
 * SyntaxHighlighter is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 * 
 * SyntaxHighlighter is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with SyntaxHighlighter.  If not, see <http://www.gnu.org/licenses/>.
 * 
 * 
 * Very simple Verilog brush,wish you will like it.
 * http://www.tyreal.net/
 */
SyntaxHighlighter.brushes.Verilog = function()
{
	var datatypes =
		//Net Type
		'wire wor wand tri trior triand trireg tri1 tri0 supply0 supply1 '+
		//Register Type
		'reg integer time real realtime '+
		//Gate Primitives
		'and nand or nor xor xnor buf not bufif0 bufif1 notif0 notif1 pullup pulldown pmos nmos cmos tran tranif1 tranif0 '+
		'parameter event';
	var keywords =
		//Module
		'module input output inout specify endspecify endmodule '+
		//Decalrations
		'task endtask function endfunction '+
		//Parallel Statements	 
		'assign initial always defparam '+
		//Sequential Statements
		'begin end if else case casex casez default endcase forever repeat while for wait fork join disable assign deassign posedge negedge '+
		//Specify Block Statements
		'specparam';


this.regexList = [
	{ regex: SyntaxHighlighter.regexLib.singleLineCComments,	css: 'color1' },			// one line comments
	{ regex: SyntaxHighlighter.regexLib.multiLineCComments,		css: 'color1' },			// multiline comments
	{ regex: SyntaxHighlighter.regexLib.doubleQuotedString,		css: 'string' },			// strings
	{ regex: SyntaxHighlighter.regexLib.singleQuotedString,		css: 'string' },			// strings
	{ regex: /^ *`.*/gm,						css: 'preprocessor' },
	{ regex: /\b\d+\'?[oObBdDhH]?[0-9xXzZA-Fa-f]*/g,		css: 'value' },
	{ regex: /\$\w+/g,						css: 'functions bold' },
	{ regex: new RegExp(this.getKeywords(datatypes), 'gm'),		css: 'variable bold' },
	{ regex: new RegExp(this.getKeywords(keywords), 'gm'),		css: 'keyword bold' }
	];
};

SyntaxHighlighter.brushes.Verilog.prototype = new SyntaxHighlighter.Highlighter();
SyntaxHighlighter.brushes.Verilog.aliases = ['verilog'];