SystemVerilogお勉強(3)

もうひとつのサンプルコード。

simple_export

exportを試してみましょう。

$ cp -R /opt/Xilinx/Vivado/2017.2/examples/xsim/systemverilog/dpi/simple_export .
$ cd simple_export

ソースコードを見てみよう

function.c

function.cはsimple_importと同じですね。

#include "dpi.h"

int cFunc(int x)
{
  return svFunc(x) ;
}

file.sv

file.svはsvFuncをC側で実行できるようにして、cFuncをSystemVerilog側で実行すると・・・

ここでExportとImportを両方、試してるじゃないか！

サンプルってこれだけていいじゃないんですかね？

module TOP();

  export "DPI-C" function svFunc ;

  int svValue ;

  function int svFunc(input int x) ;
    svValue = x + 1 ;
    return svValue + 3 ;
  endfunction

  import "DPI-C" function int cFunc(input int x) ;

  int result ;

  initial
  begin
    svValue = 15 ;
    result = cFunc(3) ;
    if (svValue != 4)
    begin
      $display("FAILED") ;
      $finish ;
    end
    if (result == 7)
      $display("PASSED") ;
    else
      $display("FAILED") ;
  end

endmodule

いざ、実行！

importと同じくrun.cshのコマンドを叩くと・・・

xvlog -sv file.sv
xelab TOP -dpiheader dpi.h
xsc function.c
xelab TOP -sv_lib dpi -R

以下、結果。

$ xvlog -sv file.sv
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/simple_export/file.sv" into library work
INFO: [VRFC 10-311] analyzing module TOP
$ xelab TOP -dpiheader dpi.h
Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab TOP -dpiheader dpi.h
Multi-threading is on. Using 10 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Exiting after writing out the dpi header file dpi.h.
$ xsc function.c
Multi-threading is on. Using 10 slave threads.
Running compilation flow
Done compilation
Done linking: "/simple_export/xsim.dir/xsc/dpi.so"
$ xelab TOP -sv_lib dpi -R
Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab TOP -sv_lib dpi -R
Multi-threading is on. Using 10 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module work.TOP
Built simulation snapshot work.TOP

****** Webtalk v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source /simple_export/xsim.dir/work.TOP/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] '/simple_export/xsim.dir/work.TOP/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Mon Jul 31 11:21:09 2017. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Mon Jul 31 11:21:09 2017...

****** xsim v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source xsim.dir/work.TOP/xsim_script.tcl
# xsim {work.TOP} -autoloadwcfg -runall
Vivado Simulator 2017.2
Time resolution is 1 ps
run -all
PASSED
exit
INFO: [Common 17-206] Exiting xsim at Mon Jul 31 11:21:17 2017...
$

こちらもPASSEDが表示されたからいいのかしら・・・。

Tweet write: 2017/07/31/ 22:17:32